This invention relates generally to logarithmic amplifiers, and, more particularly, to a multi-stage logarithmic amplifier of the "progressive-compression" type including a multi-stage detector circuit.
Progressive-compression type logarithmic amplifiers are well-known in the art and are widely employed to provide high-speed response to signals having a large dynamic range, often in applications where an automatic gain control circuit would be inapplicable due to its slow response to changes in signal amplitude. Progressive-compression type logarithmic amplifiers synthesize a logarithmic function to progressive compression of an input signal over many amplifier stages (typically 5 to 10). Each amplifier stage has a relatively low linear gain, (typically 2 to 4) up to some critical level. Above the critical level the incremental gain of the amplifier stage is reduced, and in some cases is zero.
An example of a prior art progressive-compression type logarithmic amplifier is shown in FIG. 1. The logarithmic amplifier 10 of FIG. 1 includes a plurality of serially connected gain stages 14-20. The gain stages produce an output signal V.sub.OUT at an output terminal 22 that is proportional to the logarithm, i.e., the decibel magnitude, of an input signal V.sub.IN received at the logarithmic amplifier input 12.
The logarithmic amplifier also includes a plurality of detector cells 24-32. The detector cells 26-32 are coupled to the output of a corresponding gain stage to determine the signal strength of a signal produced thereby. An additional detector 24 as shown in FIG. 1, can be coupled to the input of the first gain stage 14 to determine the signal strength of the input signal V.sub.IN. Each of the detector cells produce an output signal that is proportional to the signal strength detected thereby. The outputs of the detectors are then summed together to determine the overall signal strength of the signal generated by the logarithmic amplifier 10. In the embodiment shown in FIG. 1, the detector cells produce a current output, by using a transconductance element, therefore the summation is accomplished by coupling the detector outputs to a current bus 34. The current I.sub.LOG produced on the current bus 34 is a logarithmic function of the signal strength of the input signal V.sub.IN. This current I.sub.LOG is then converted to a voltage V.sub.RSSI, where RSSI stands for received signal strength indicator, by coupling a load resistor 38 between the current bus 34 and ground. Alternatively, the resistor can be implemented by a transresistance stage. It should be noted that detector stages 24-32 can be implemented having a voltage output. In that case, a separate voltage summing circuit, rather than a simple current bus, is required to add the detector voltage outputs.
The output signal V.sub.RSSI produced by the detector cells, as the name indicates, is an indication of the received signal strength of the input signal V.sub.IN. In portable phone applications, for example, this signal V.sub.RSSI can be used to modulate both the power of the handset as well as the transmitter station. When the signal V.sub.RSSI indicates that the received signal strength is low, the hand-held receiver can indicate to the station that more transmit power is required. At the same time, transmit power should be kept at a minimum to minimize CO-channel interference which is interference produced by two stations covering adjacent geographical regions transmitting at the same frequency. The signal V.sub.RSSI can also be used by the handset to modulate its transmit power based on the signal level. The handset transmit power is roughly inversely proportional to the V.sub.RSSI signal level. The handset transmit power must also be kept to a minimum to avoid excessive power consumption in the handset. Minimizing the power consumption in the handset is particularly important because most handsets operate on batteries which have a finite amount of power storage.
An example of a prior art detector cell is shown in FIG. 2. The detector cell 24, which corresponds to detector cell 24 of FIG. 1, includes three transistors (Q1-Q3). The transistors are bipolar junction transistors (BJT) with the second transistor Q2 having an emitter area (De) equal to a multiple (D) of the emitter areas (e) of transistors Q1 and Q3. A first resistor R.sub.B is coupled between the bases of the first and second transistors Q1 and Q2 and a second transistor R.sub.B is coupled between the bases of transistors Q2 and Q3. The emitters of transistors Q1-Q3 are coupled to a current source supplying a current I.sub.D to the detector circuit. The collectors of Q 1 and Q3, 40 and 44, respectively, can be coupled to a load or a supply voltage, as is known in the art. The collector 42 of transistor Q2 forms the output of the detector cell. The base of transistor Q 1 forms a first input 46 of the detector cell and the base of register Q3 forms a second input 48 of the detector cell.
In operation, as a signal V.sub.0 applied to detector inputs 46 and 48 swings positive or negative, the use of the resistor divider formed by the two resistors R.sub.B results in one of the two outer transistors Q1 and Q3 conducting more heavily. The form of the resulting collector currents in transistors Q 1 and Q3 is approximately a hyperbolic cosine. Thus, the output current I.sub.OUT flowing through the second transistor Q2 is equal to the difference between the current I.sub.D and the collector currents of the transistors Q1 and Q3. The resulting output current I.sub.OUT as a function of the input signal V.sub.0 is shown in FIG. 3. As is apparent from FIG. 3, the output current I.sub.OUT is maximum when no input signal V.sub.0 is applied to the detector cell. The magnitude of the output current at this maximum point is equal to I.sub.D x(D/2+D). This behavior results in undesirable power consumption when no signal is being detected. This effect is multiplied for each one of the detector cells. The cumulative effect of this output current results in lower battery life in the handset.
Accordingly, a need remains for a detector cell that does not produce an output current when no signal is being detected.